1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, a semiconductor device manufacturing method having a multi-layered wiring structure.
2. Description of the Prior Art
In the case that wirings in a semiconductor integrated circuit device are formed of aluminum or tungsten, the photolithography method is adopted as a method of patterning an aluminum film or a tungsten film. In other words, after a resist pattern is formed on the aluminum film or the tungsten film, such patterning is carried out by removing the aluminum film or the tungsten film being not covered with the resist pattern by virtue of the dry etching. Since products are adhered onto side walls of the wiring during the step of patterning the aluminum film or the tungsten film, normally such products are removed by alkali chemicals, etc.
As other material of the wiring, copper (Cu) which has a lower resistance than the aluminum or the tungsten is requested with the miniaturization of the semiconductor integrated circuit, but it is difficult to etch a copper film by virtue of the dry etching.
Therefore, the method of patterning the copper film by the photolithography method is not normally employed. The damascene method is employed to form the copper wiring pattern.
There are two ways as the damascene method, i.e., the single damascene method in which a via layer and a wiring layer are formed by independent steps, and the dual damascene method in which the via layer and the wiring layer are formed by the same steps. During the step of forming the wirings, both methods include the steps of forming recesses in an insulating film by the dry etching method and then burying a metal into the recesses. In this case, via material or wiring material employed in the damascene method are not always limited to the copper, and other metals may be employed.
However, according to the method of forming the wirings by virtue of the damascene method, sometimes thin-film like reaction product remains around the recesses in etching the insulating film to form the recesses, and such reaction product causes various problems.
Next, formation of the recesses by the single damascene method and generation of the reaction product will be explained hereunder.
First, as shown in FIG. 1A, a second interlayer insulating film 103 made of SiO2 is formed on a first interlayer insulating film 101 in which a first via 102 made of tungsten, or the like is buried, and then a first copper wiring 104 is formed on the first via 102 and in the second interlayer insulating film 103 by the damascene method. In addition, a first silicon nitride film 105 and a third interlayer insulating film 106 made of SiO2 are formed on the second interlayer insulating film 103, and then a second via 107 made of copper is formed in the first silicon nitride film 105 and the third interlayer insulating film 106 on the first copper wiring 104.
Then, a second silicon nitride film 108 for covering the second via 107 and the third interlayer insulating film 106, a fourth interlayer insulating film 109 made of SiO2, and a reflection preventing film 110 made of silicon nitride are formed in sequence.
Then, resist 111 is coated on the reflection preventing film 110, and then a window 111a for forming the wiring is formed by exposing/developing this resist 111.
Next, as shown in FIG. 1B, when a wiring recess 112 is formed by etching the reflection preventing film 110 and the fourth interlayer insulating film 109 via the window 111a in the resist 111, reaction product 113 formed of silicon compound is adhered onto a side wall of the resist 111.
Then, when the washing of the resist 111 is carried out by using an oxygen containing gas, for example, a mixed gas of oxygen and nitrogen, silicon series reaction product 113 still remains in the neighborhood of the wiring recess 112, as shown in FIG. 1C.
If the reaction product 113 exists, a metal film is not well grown in burying a metal film such as copper, etc. into the wiring recess 112, and thus such metal film is ready to peel off.
Accordingly, a method of removing the reaction product by using a hydrofluoric acid (HF) after the resist has been removed, or removing the reaction product by introducing a fluorine compound gas in an oxygen gas in removing the resist is adopted. If CF4 is used as the fluorine compound gas, normally such CF4 is mixed in the range of 10 to 15 flow rate % relative to a total gas flow rate.
However, in recent such a tendency is increased that the increase in the interwiring capacitance becomes remarkable with the miniaturization of the semiconductor integrated circuit and thus an insulating film with a low dielectric constant is employed as the interlayer insulating film per se.
FSG (Fluoro-Silicate Glass) as such insulating film with the low dielectric constant has various problems in adhesiveness, posttreatment resistance, etching performance, etc. rather than other silicon compound films. Thus, the situation that the hydrofluoric acid and the fluorine compound gas, as described above, cannot be applied to the FSG is brought about.
As one of the problems, generation of unevenness on the side wall of the wiring recess or the side wall of the via hole may be pointed out. An example will be mentioned with reference to FIG. 2 hereunder.
First, as shown in FIG. 2A, the second interlayer insulating film 103 made of SiO2 is formed on the first interlayer insulating film 101 in which the first via 102 made of tungsten, or the like is buried, and then the first copper wiring 104 is formed on the first via 102 and in the second interlayer insulating film 103 by the damascene method. In addition, a first silicon nitride film 115, a first FSG film 116, a first SiO2 film 117, a second silicon nitride film 118, a second FSG film 119, and a second SiO2 film 120 are formed in sequence on the second interlayer insulating film 103. Then, a reflection preventing film 121 made of silicon nitride is formed on the second SiO2 film 120.
Then, an opening 122 having a via shape is formed over the first copper wiring 104 by patterning the reflection preventing film 121, the second SiO2 film 120, the second FSG film 119 by means of the photolithography method.
In turn, resist 123 is coated on the reflection preventing film 121, and then a window 123a is formed in a second copper wiring forming portion by exposing/developing this resist 123. Then, a second wiring recess 125 is formed by etching vertically respective films from the reflection preventing film 121 to the second FSG film 119 via the window 123a in the resist 123. At the same time, respective films from the second silicon nitride film 118 to the first FSG film 116 below the opening 122 are also etched upon above etching, and thus a via hole 124 having the same diameter as the opening 122 is formed.
Then, as shown in FIG. 2B, a fence-like reaction product 126, i.e., a silicon compound, still remains in the neighborhood of the second wiring recess 125 when the resist 123 is removed.
As described above, if the hydrofluoric acid or the fluorine compound gas is employed to remove the reaction product 126, unevenness is caused on the side walls of the wiring recess 125 and the via hole 124, as shown in FIG. 2C. This is because respective etching rates of FSG, SiO2, and silicon nitride against the hydrofluoric acid or the fluorine compound gas are different. The etching rates against the hydrofluoric acid or the fluorine compound gas are high in the order of FSG, SiO2, and silicon nitride.
In this manner, if the metal such as tantalum nitride, copper, etc. is buried in the wiring recess 125 and the via hole 124 on the side wall of which the unevenness is caused, metal burying failure such as void, etc. is caused easily.
As described above, the fence of the reaction product which is generated in forming the recess in the insulating film causes peeling-off of the metal film which is buried in the wiring recess, and also the hydrofluoric acid or the fluorine compound gas employed to remove such reaction product generates the unevenness on the side wall of the recess to thus cause the metal burying failure.
Moreover, in order to prevent oxidation of the copper which is buried in the wiring recess and the via hole and diffusion of the copper into the insulating film, sometimes a silicon nitride film or a silicon nitride oxide film is formed under the wiring recess and the via hole. In this case, if the fluorine compound gas such as CF4 is employed to remove the reaction product, the silicon nitride film or the silicon nitride oxide film is etched to some extent. As a result, there is such a possibility that the copper wiring or the copper via below the wiring recess and the via hole is oxidized.
It is an object of the present invention to provide a semiconductor device manufacturing method including the step of preventing reduction in film thickness of a silicon nitride film or a silicon nitride oxide film in removing fence-like reaction residues not to cause unevenness on side walls of holes when the reaction residues generated in forming recesses is removed.
According to the present invention, the wiring recess is formed by etching the insulating film while using the resist as a mask, then the resist is removed, and then the reaction product generated by etching the insulating film is removed by the plasma of the inactive gas. As the inactive gas being introduced, either a mixed gas of the inactive gas and the gas except halogen or the single inactive gas may be employed.
Therefore, the inner surface of the wiring recess and the inner surface of the via hole formed under the wiring recess can be prevented from being etched by the halogen gas in removing the reaction product, and thus generation of the unevenness on these inner surfaces can be suppressed. In addition, since the etching stopper film formed under the insulating film can be prevented from being etched by halogen, there is no possibility that the via or the wiring existing under the etching stopper film is exposed and oxidized.